1/10 july 2001 n high speed: t pd = 5.8 ns (typ.) at v cc = 3.3 v n compatible with ttl outputs n low power dissipation: i cc = 4 m a (max.) at t a =25c n low noise: v olp = 0.5v (typ.) at v cc = 3.3v n 75 w transmission line driving capability n symmetrical output impedance: |i oh | = i ol = 12ma (min) at v cc = 3.0 v n pci bus levels guaranteed at 24 ma n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 2v to 3.6v (1.2v data retention) n pin and function compatible with 74 series 573 n improved latch-up immunity description the 74lvq573 is a low voltage cmos octal d-type latch with 3 state outputs non inverting fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. it is ideal for low power and low noise 3.3v applications. these 8 bit d-type latch are controlled by a latch enable input (le) and an output enable input (oe ). while the le input is held at a high level, the q outputs will follow the data input precisely. when the le is taken low, the q outputs will be latched precisely at the logic level of d input data. while the (oe ) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. in order to enhance pc board layout, the 74lvq573 offers a pinout having inputs and outputs on opposite side of the package. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74lvq573 low voltage cmos octal d-type latch with 3 state outputs non inverting pin connection and iec logic symbols order codes package tube t & r sop 74LVQ573M 74LVQ573Mtr tssop 74lvq573ttr tssop sop
74lvq573 2/10 input and output equivalent circuit pin description truth table x : dont care z : high impedance * : q outputs are latched at the time when the le input is taken low logic level logic diagram pin no symbol name and function 1oe 3 state output enable input (active low) 2, 3, 4, 5, 6, 7, 8, 9 d0 to d7 data inputs 12, 13, 14, 15, 16, 17, 18, 19 q0 to q7 3-state latch outputs 11 le latch enable input 10 gnd ground (0v) 20 v cc positive supply voltage inputs output oe le d q hxxz l l x no change* lhll lhhh
74lvq573 3/10 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied recommended operating conditions 1) truth table guaranteed: 1.2v to 3.6v 2) v in from 0.8v to 2v dc specifications 1) maximum test duration 2ms, one output loaded at time 2) incident wave switching is guaranteed on transmission lines with impedances as low as 75 w symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output current 50 ma i cc or i gnd dc v cc or ground current 400 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage (note 1) 2 to 3.6 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c dt/dv input rise and fall time v cc = 3.0v (note 2) 0 to 10 ns/v symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 3.0 to 3.6 2.0 2.0 2.0 v v il low level input voltage 0.8 0.8 0.8 v v oh high level output voltage 3.0 i o =-50 m a 2.9 2.99 2.9 2.9 v i o =-12 ma 2.58 2.48 2.48 i o =-24 ma 2.2 2.2 v ol low level output voltage 3.0 i o =50 m a 0.002 0.1 0.1 0.1 v i o =12 ma 0 0.36 0.44 0.44 i o =24 ma 0.55 0.55 i i input leakage current 3.6 v i = v cc or gnd 0.1 1 1 m a ioz high impedance output leakage current 3.6 v i = v ih or v il v o = v cc or gnd 0.25 2.5 5.0 m a i cc quiescent supply current 3.6 v i = v cc or gnd 44040 m a i old dynamic output current (note 1, 2) 3.6 v old = 0.8 v max 36 25 ma i ohd v ohd = 2 v min -25 -25 ma
74lvq573 4/10 dynamic switching characteristics 1) worst case package. 2) max number of outputs defined as (n). data inputs are driven 0v to 3.3v, (n-1) outputs switching and one output at gnd. 3) max number of data inputs (n) switching. (n-1) switching 0v to 3.3v. inputs under test switching: 3.3v to threshold (v ild ), 0v to threshold (v ihd ), f=1mhz. ac electrical characteristics (c l = 50 pf, r l = 500 w , input t r = t f = 3ns) 1) skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch- ing in the same direction, either high or low (t oslh = |t plhm - t plhn |, t oshl = |t phlm - t phln |) 2) parameter guaranteed by design (*) voltage range is 3.3v 0.3v symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v olp dynamic low voltage quiet output (note 1, 2) 3.3 c l = 50 pf 0.5 0.8 v v olv -0.8 -0.6 v ihd dynamic high voltage input (note 1, 3) 3.3 2 v v ild dynamic low voltage input (note 1, 3) 3.3 0.8 v symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t plh t phl propagation delay time le to q 2.7 7.2 11.5 13.5 15.5 ns 3.3 (*) 5.8 9.0 10.5 12.0 t plh t phl propagation delay time d to q 2.7 7.2 11.5 13.5 15.5 ns 3.3 (*) 5.8 9.0 10.5 12.0 t plz t phz output disable time 2.7 8.7 14.0 16.0 18.5 ns 3.3 (*) 7.4 11.5 13.5 15.5 t pzl t pzh output enable time 2.7 8.5 14.0 16.0 18.5 ns 3.3 (*) 7.5 11.5 13.5 15.5 t w le pulse width high 2.7 2.0 5.0 6.0 6.0 ns 3.3 (*) 1.5 4.0 4.0 4.0 t sl t sh setup time d to le high or low 2.7 0.0 4.0 4.5 4.5 ns 3.3 (*) 0.0 3.0 3.0 3.0 t hl t hh hold time d to le, high or low 2.7 0.0 1.5 1.5 1.5 ns 3.3 (*) 0.0 1.5 1.5 1.5 t oslh t oshl output to output skew time (note1, 2) 2.7 0.5 1.0 1.0 1.0 ns 3.3 (*) 0.5 1.0 1.0 1.0
74lvq573 5/10 capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc /n (per latch) test circuit c l = 50pf or equivalent (includes jig and probe capacitance) r l = r 1 = 500 w or equivalent r t = z out of pulse generator (typically 50 w ) symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 3.3 4 pf c out output capacitance 3.3 8 pf c pd power dissipation capacitance (note 1) 3.3 f in = 10mhz 10 pf test switch t plh , t phl open t pzl , t plz 2v cc t pzh , t phz open
74lvq573 6/10 waveform 1: le to qn propagation delays, le minimun pulse width, dn to le setup and hold times (f=1mhz; 50% duty cycle)
74lvq573 7/10 waveform 2: output enable and disable times (f=1mhz; 50% duty cycle) waveform 3: dn to qn propagation delay time (f=1mhz; 50% duty cycle)
74lvq573 8/10 dim. mm. inch min. typ max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45 (typ.) d 12.60 13.00 0.496 0.512 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 m 0.75 0.029 s8 (max.) so-20 mechanical data po13l
74lvq573 9/10 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 6.4 6.5 6.6 0.252 0.256 0.260 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop20 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0087225c
74lvq573 10/10 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com
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